A known method used to debug a processor utilises means for observing the program flow during operation of the processor. With systems having off-chip cache, program observability is relatively straight forward by using probes. However, observing the program flow of processors having cache integrated on-chip is much more problematical since most of the processing operations are performed internally within the chip.
Typically, processor based systems are debugged using an In- Circuit-Emulator (ICE) device. The ICE is connected to pins of the processor's Central Processing Unit (CPU) socket (and may replace the CPU itself) and under operator control, executes either the normal application program or special debug software programs. The ICE halts execution when specific events occur, or when manually requested by the operator, and provides the operator with internal processor status information (such as register states) or system status information (such as memory or input/output states).
In order to debug a processor system, the ICE device must operate with the same electrical parameters as the processor system. For example, the connection between the ICE and the processor pins must comply with the processor's operating frequency. As processors become more powerful, they operate at higher frequencies and have higher pin counts. Connection of the ICE cable to the processor increases the capacitance on the processor pins, with the result that it is more difficult to maintain the high operating frequencies At high operating frequencies (for example above 50 MHz), the ICE cannot capture data from the processor pins due to the large capacitance thereon.
Another disadvantage of ICE devices is the high expense involved in their implementation. The ICE comprises a significantly large amount of expensive hardware such as a CPU and surrounding buffers and trace buffers to which data is captured from the processor. In addition, a special interface, that is capable of transferring signals at such high frequencies, is normally required.
A further disadvantage of using ICE devices to test cached processors lies in the fact that ICE devices can generally only be used with through-hole packages, such as Pin Grid Array (PGA) Dual-in-line packages, since problems arise when trying to connect an ICE to a system designed with modern types of packages, such as Plastic Leadless Chip Carrier (PLCC) packages, Ceramic Quadrupole Flat Packages (CQFP), Plastic Quadrupole Flat Packages (PQFP) and Tape Automated Bonding (TAB) packages.
A cached processor can also be tested by coupling a test station to a dedicated port of the CPU via cables. However, this arrangement also suffers from problems at high frequencies: the cable must be as extremely short for high operating frequencies.
It is also known to use a dedicated FIFO register in the cached processor to record the last five executed instructions. Such a register is expensive to implement and its small size is limiting.
There is therefore a need for a cached processor having inexpensive means which allows the real time capture of data in the cached processor for debug purposes and which can be used at high frequencies and with any type of packages.